Integrated circuits (ICs) are formed on semiconductor substrates using different processing techniques, known in the art, to produce transistors, interconnection elements, and the like. In order to electrically connect transistors on the semiconductor substrate, conductive vias, trenches and interconnects are formed in the dielectric materials as part of the integrated circuit. These vias, trenches and electrical interconnections combine electrical signals and power between transistors, internal circuits of the IC, and circuits external to the integrated circuit, for example.
The semiconductor industry is constantly working to improve the quality, reliability and throughput of integrated circuits based in part upon consumer demand for higher quality devices. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the electrical device. Copper is increasingly becoming the material of choice for forming conductive interconnections on integrated circuit devices. This is due, in large part, to the superior electrical characteristics of copper as compared to other materials, e.g., aluminum, previously used to form such interconnections. Copper is not readily etched by chemical processes and thus fabrication processes such as single damascene and dual damascene, have been utilized to create copper conductive interconnections. In general, such methods involve forming a patterned layer of insulating material having multiple openings, such as trench interconnect lines or interconnect vias, formed therein, forming a barrier metal layer above the patterned insulating layer and in the openings, forming a copper seed layer above the barrier metal layer, performing an electroplating process to deposit a bulk copper layer above the copper seed layer and, thereafter, performing one or more chemical mechanical polishing processes to remove the excess copper and barrier material from above the patterned insulating layer.
Damascene interconnection processes for semiconductor devices are replacing conventional deposition and etch processes. Traditionally, metal films have been deposited and patterned using photolithography to pattern metal interconnects within a semiconductor substrate. As conductive lines are patterned closer and closer together and as interconnections shrink, it becomes more and more difficult to accurately pattern the conductive lines and form the conductive interconnects using the conventional layered deposition and patterning processes that do not suffer in some way from electrical or mechanical problems. Often, solving one problem can result in creating yet another, different problem.
For example, etch stop layering techniques are well known by those of ordinary skill in the art. In one process a special plasma treatment is carried out before the etch stop layer (e.g., silicon nitride) deposition since copper is not self passivating as is aluminum to form an oxide (e.g., aluminum oxide, and the like) that if not cleaned off can result in poor adhesion between the copper and the etch stop layer silicon nitride, for example. With weak adhesion, electrons can diffuse along copper and silicon nitride interface to significantly degrade electro-migration lifetime, for example.
An example of a damascene process is described in U.S. Pat. No. 6,800,494; wherein the process is depicted in prior art FIGS. 1-5. The following is a brief discussion of an illustrative prior art process flow for forming interconnections in an integrated circuit device. It is to be appreciated that numerous prior art methods exist for creating damascene structures and the following method illustrates but one such method and its associated problems. These problems are common place in many damascene techniques.
As shown in prior art FIG. 1, a transistor 22 is formed above a substrate 20 between isolation regions 26. The transistor 22 is comprised of source/drain regions 24. Also depicted in prior art FIG. 1 is a patterned layer of insulating material 25 having a plurality of conductive trenches or contacts 27 formed therein. As will be recognized by those skilled in the art, the conductive contacts 27 provide electrical contact to the source/drain regions 24 of the transistor 22. The materials used to form the components depicted in FIG. 1, as well as the methods of making such components, are generally well-known to those skilled in the art and will not be described herein in any greater detail. For example, the conductive contacts 27 may be comprised of a variety of materials, e.g., tungsten, and they may be formed by a variety of known techniques. The size, shape and number of the conductive contacts 27 may also vary. Although not depicted in the drawings, a barrier/glue layer of metal, e.g., titanium may be formed in the openings in the patterned layer of insulating material 25 prior to forming the conductive contacts 27.
Additionally, although the present invention is initially described in the context of forming conductive interconnections 36A (see prior art FIG. 5) that contact the conductive contacts 27, those skilled in the art, after reading the entirety of the present application, will understand that the methods of the present invention may be employed to form conductive interconnections at any level of an integrated circuit device using a variety of techniques, such as single or dual damascene integration techniques.
Initially, a patterned layer of insulating material 28, having a plurality of openings 30 formed therein, is formed above the layer of insulating material 25 and the conductive contacts 27. The patterned layer of insulating material 30 may be comprised of a high-K (K>5) material, a low-K (2.5<K<5.0) material, or an ultra low-K (K<2.5) material, and it may be formed by a variety of processing methods, e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on dielectric (SOD), etc. Alternatively, a multi-film composite stack could be used which would include combinations of the above films and could include an etch stop layer, a middle etch stop, a cap layer, a pore seal layer, etc. The openings 30 in the patterned layer of insulating material 28 may be formed by performing one or more etching processes in an etch tool (not shown). Thereafter, the substrate 20, with the patterned layer of insulation material 28 formed thereabove, is positioned in the vacuum isolated tool where a degas process, an etch/clean process, a barrier metal deposition process, and a copper seed deposition process are performed.
More specifically, the degas process is performed in a degas chamber, wherein the wafer 20 is heated under vacuum to a temperature range of approximately 150-450° C. for approximately 30-240 seconds. The purpose of the degas process is to remove, outgas or drive off a variety of residual materials that may be present on or in the patterned insulating material 28, such as water (as H2O or OH), CO, CO2, F2, hydrocarbons, etc. Then, the wafer 20 is vacuum-transferred to the etch/clean chamber, where any residual contamination, hydrocarbons, polymers or oxides covering any important contact regions are removed by sputter etching the wafer 20.
Once the wafer 20 has been cleaned in the etch/clean chamber, the wafer 20 is transferred under vacuum to the barrier metal deposition chamber, where a process is performed to deposit the barrier metal layer 32 shown in prior art FIG. 2. The barrier metal layer 32 is deposited above the patterned insulating layer 28 and in the openings 30 that were cleaned in the previous etch/clean chamber 14. The barrier metal layer 32 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other techniques known to those skilled in the art. This barrier metal layer 32 may be comprised of a variety of materials, e.g., tantalum, tantalum nitride, titanium, titanium nitride, titanium nitride silicon, titanium silicon nitride, tungsten, tungsten nitride, tungsten carbon nitride, etc., and it may have a thickness ranging from approximately 0.1-60 nm. The purpose of the barrier metal layer 32 is to, among other things, provide adhesion to the interlayer dielectric layers, provide wetting to the copper seed layer, and prevent migration of the copper material that forms the conductive interconnection 36A into unwanted areas of the integrated circuit device. Ideally, this barrier metal layer 32 will be as thin as possible, while still maintaining its ability to perform its intended function.
Next, the wafer 20 is sent, under vacuum, to the copper seed layer deposition chamber wherein the copper seed layer 34 is deposited above the barrier metal layer 32, as depicted in prior art FIG. 3. The process performed in the copper seed layer deposition chamber may be a PVD, CVD or ALD process, or any other technique known to those skilled in the art for forming such layers. The thickness of the copper seed layer 34 may range from approximately 20-200 nm. The copper seed layer 34 may be pure copper or it may be comprised of a copper alloy, such as copper tin, copper magnesium, copper chromium, copper calcium, etc. After the copper seed layer 34 is deposited, the wafer 20 may be removed from the barrier/seed tool and an electroplating process may be performed to form a bulk copper layer 36 above the wafer 20, as shown in prior art FIG. 4. The techniques and method used to form the bulk copper layer 36 using electroplating processes are well-known to those skilled in the art. After the bulk copper layer 36 is formed, an anneal process may be performed, and one or more chemical mechanical polishing operations may be performed to remove the excess portions of the bulk copper layer 36, the copper seed layer 34 (to the extent it is distinguishable from the bulk copper layer 36) and the barrier metal layer 32 from above the surface 29 of the patterned layer of insulating material 28 to thereby result in the definition of the copper interconnections 36A as shown in prior art FIG. 5.
FIGS. 6A and 6B illustrate yet another conventional prior art method 600 for fabricating a dual damascene structure as disclosed in U.S. Pat. No. 6,767,827. Referring initially to FIG. 6A, the method 600 comprises front end processing 630 which may include acts 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 624, 626 and 628. The method begins at 602 wherein a substrate has a dielectric layer having one or more conductive structures residing therein, such as copper interconnects. At 602 an etch stop layer is formed over the substrate. At 604 a photoresist can then be formed over the etch stop layer (ESL) at 604, for example, via a spin-coating process. The photoresist is also patterned at 604, for example, by selectively exposing the photoresist to radiation followed by development thereof according to photolithography techniques. The portion of the ESL exposed by the patterned photoresist is then patterned at 606 using the patterned photoresist as a mask. The ESL is patterned at 606 via a dry etch process that is substantially selective to the underlying substrate material which may be, for example, copper or tungsten. The patterned photoresist is then removed at 608.
The prior art method 600 of FIG. 6A continues at 610, wherein a first inter-layer dielectric (ILD) is formed over the patterned ESL. A mid-etch stop layer (MSL) at 612, is then formed on or over a first inter-layer dielectric (ILD) at 612. A second ILD can then be formed over the first MSL at 614, for example. As shown in FIG. 6A, two cap layers are formed over the patterned second ESL in succession at 616. A photoresist layer is then formed over the second cap layer at 618, and the top (or second) cap layer is patterned at 620 to have an opening therethrough that generally corresponds to the opening within the underlying ESL. The remaining photoresist is subsequently removed at 620 as well. In one example, the opening is larger than the ESL opening, wherein the ESL opening generally corresponds to a via opening size while the top cap layer opening generally corresponds to a trench opening size, as will be further appreciated by those of skill in the art.
At 622, another photoresist is formed and patterned over the first cap layer and used to form an opening in the lower second cap layer at 624 (the first cap layer), wherein the opening therein is smaller than the opening in the second cap layer. A second ILD is then patterned at 626 using the patterned photoresist (if not removed) and the opened first cap layer as a mask to define a via opening (generally corresponding to the opening in the ESL). The first cap layer and exposed MSL are patterned concurrently at 628, followed by concurrent patterning of the first and second ILD layers. The trench width is defined by the cap layers and the via width is defined by the opened MSL. At 628 the front end processing 630 (see bracketed processes in FIG. 6A) in the prior art approach is completed. It should be appreciated that the term “front end processing” is arbitrarily defined and could include additional processes or delete some of the acts shown. As mentioned supra, the process 630 described was a current method for front-end processing of a single or dual damascene device described in U.S. Pat. No. 6,767,827.
The prior art process 600 may then continue at 632 by the deposition of a conductive material, for example, copper. Now described is the current technology for backend-of-line processing (not related to U.S. Pat. No. 6,767,827 discussed supra) and some of the associated problems with the prior art approach that the invention overcomes. In the current generic single and dual damascene (inlaid) backend-of-line (BEOL) process flows, electrochemical copper plated (ECP) films are deposited, at 632 in FIG. 6B, within the oxide via and trench structures and over the full wafer surface. This is followed by a copper anneal involving H2 and N2 at 634, followed by a chemical mechanical polish (CMP) process 636 to define and isolate the copper wiring within the dielectric for a given product pattern layout. After the copper wiring is defined, a dielectric capping layer, diffusion barrier layer, and etch stop layer (ESL) is deposited at 638 followed by subsequent BEOL processing at 640 to complete the full process integration. This copper dielectric interface has been extensive studied and characterized in the literature. However, the following manufacturing issues have been observed, e.g., interface adhesion failures, delamination, Cu hillock defects, interlayer dielectric (ILD) nodules, metal sheet resistance variation, voltage ramped dielectric breakdown (VRDB) leakage, time dependent dielectric breakdown (TDDB) leakage, and pad peeling.
Therefore, a method and process for damascene processing is desired that allows for increased reliability of the memory devices. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.